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1. general description the lpc1311/13/42/43 are arm cortex-m3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. the arm cortex-m3 is a next generation core that offe rs system enhancements such as enhanced debug features and a higher level of support block integration. the lpc1311/13/42/43 operate at cpu frequencies of up to 72 mhz. the arm cortex-m3 cpu incorporates a 3-stage pipe line and uses a harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. the arm cortex-m3 cpu also includes an internal prefetch unit that supports speculative branching. the peripheral complement of the lpc1311/ 13/42/43 includes up to 32 kb of flash memory, up to 8 kb of data memory, usb device (lpc1342/43 only), one fast-mode plus i 2 c-bus interface, one uart, four general pur pose timers, and up to 42 general purpose i/o pins. remark: the lpc1311/13/42/43 series consists of the lpc1300 series (parts lpc1311/13/42/43) and the lpc1300l series (parts lpc1311/01 and lpc1313/01). the lpc1300l series features the following enhancements over the lpc1300 series: ? power profiles with lowe r power consumption in active and sleep modes. ? four levels for bod forced reset. ? second ssp controller (l pc1313fbd48/01 only). ? windowed watchdog timer (wwdt). ? internal pull-up resistors pull up pins to full v dd level. ? programmable pseudo open-drain mode for gpio pins. 2. features and benefits ? arm cortex-m3 processor, running at frequencies of up to 72 mhz. ? arm cortex-m3 built-in nested vector ed interrupt controller (nvic). ? 32 kb (lpc1343/13)/16 kb (lpc1342)/8 kb (lpc1311) on-chip flash programming memory. ? 8 kb (lpc1343/13)/4 kb (lpc1342/11) sram. ? in-system programming (isp) and in-application programming (iap) via on-chip bootloader software. ? selectable boot-up: uart or usb (usb on lpc1342/43 only). ? on lpc1342/43: usb msc and hid on-chip drivers. lpc1311/13/42/43 32-bit arm cortex-m3 microcontrol ler; up to 32 kb flash and 8 kb sram; usb device rev. 5 ? 6 june 2012 product data sheet
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 2 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller ? serial interfaces: ? usb 2.0 full-speed device controller with on-chip phy for device (lpc1342/43 only). ? uart with fractional baud rate generation, modem, internal fifo, and rs-485/eia-485 support. ? ssp controller with fifo and mu lti-protocol capabilities. ? additional ssp controller on lpc1313fbd48/01. ? i 2 c-bus interface supporting full i 2 c-bus specification and fast-mode plus with a data rate of 1 mbit/s with multiple address reco gnition and monitor mode. ? other peripherals: ? up to 42 general purpose i/o (gpio) pi ns with configurable pull-up/pull-down resistors. ? four general purpose counter/timers with a total of four capture inputs and 13 match outputs. ? programmable watchdog timer (wdt). ? programmable windowed watchdog timer (wwdt) on lpc1311/01 and lpc1313/01. ? system tick timer. ? serial wire debug and serial wire trace port. ? high-current output driver (20 ma) on one pin. ? high-current sink drivers (20 ma) on two i 2 c-bus pins in fast-mode plus. ? integrated pmu (power management unit) to minimize power consumption during sleep, deep-sleep, and deep power-down modes. ? power profiles residing in boot rom allowin g to optimize performance and minimize power consumption for any given application through one simple function call. (lpc1300l series, on lpc1311/01 and lpc1313/01 only.) ? three reduced power modes: sleep, deep-sleep, and deep power-down. ? single power supply (2.0 v to 3.6 v). ? 10-bit adc with input multiplexing among 8 pins. ? gpio pins can be used as edge and level sensitive interrupt sources. ? clock output function with divider that ca n reflect the system oscillator clock, irc clock, cpu clock, or the watchdog clock. ? processor wake-up from deep-sleep mode via a dedicated start logic using up to 40 of the functional pins. ? brownout detect with four separate thresholds for interrupt and one threshold for forced reset (four thresholds for forced reset on the lpc1311/01 and lpc1313/01 parts). ? power-on reset (por). ? integrated oscilla tor with an operating ra nge of 1 mhz to 25 mhz. ? 12 mhz internal rc oscillator trimmed to 1 % accuracy over the entire temperature and voltage range that can optionally be used as a system clock. ? programmable watchdog osc illator with a frequency range of 7.8 khz to 1.8 mhz. ? system pll allows cpu operation up to the maximum cpu rate without the need for a high-frequency crystal. may be run from th e system oscillator or the internal rc oscillator. ? for usb (lpc1342/43), a second, dedicated pll is provided. ? code read protection (crp) with different security levels.
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 3 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller ? unique device serial number for identification. ? available as 48-pin lqfp package and 33-pin hvqfn package. 3. applications ? emetering ? lighting ? alarm systems ? white goods 4. ordering information 4.1 ordering options table 1. ordering information type number package name description version lpc1311fhn33 hvqfn33 hvqfn33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 7 0.85 mm n/a lpc1311fhn33/01 hvqfn33 hvqfn33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 7 0.85 mm n/a lpc1313fhn33 hvqfn33 hvqfn33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 7 0.85 mm n/a lpc1313fhn33/01 hvqfn33 hvqfn33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 7 0.85 mm n/a lpc1313fbd48 LQFP48 LQFP48: plastic low prof ile quad flat package; 48 leads; body 7 7 1.4 mm sot313-2 lpc1313fbd48/01 LQFP48 LQFP48: plastic low pr ofile quad flat package; 48 leads; body 7 7 1.4 mm sot313-2 lpc1342fhn33 hvqfn33 hvqfn33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 7 0.85 mm n/a lpc1342fbd48 LQFP48 LQFP48: plastic low prof ile quad flat package; 48 leads; body 7 7 1.4 mm sot313-2 lpc1343fhn33 hvqfn33 hvqfn33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 7 0.85 mm n/a lpc1343fbd48 LQFP48 LQFP48: plastic low prof ile quad flat package; 48 leads; body 7 7 1.4 mm sot313-2 table 2. ordering option s for lpc1311/13/42/43 type number flash total sram usb power profiles uart rs-485 i 2 c/ fast+ ssp adc channels pins package lpc1311fhn33 8 kb 4 kb - no 1 1 1 8 33 hvqfn33 lpc1311fhn33/01 8 kb 4 kb - yes 1 1 1 8 33 hvqfn33 lpc1313fhn33 32 kb 8 kb - no 1 1 1 8 33 hvqfn33 lpc1313fhn33/01 32 kb 8 kb - yes 1 1 1 8 33 hvqfn33 lpc1313fbd48 32 kb 8 kb - no 1 1 1 8 48 LQFP48 lpc1313fbd48/01 32 kb 8 kb - yes 1 1 2 8 48 LQFP48
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 4 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller lpc1342fhn33 16 kb 4 kb device no 1 1 1 8 33 hvqfn33 lpc1342fbd48 16 kb 4 kb device no 1 1 1 8 48 LQFP48 lpc1343fhn33 32 kb 8 kb device no 1 1 1 8 33 hvqfn33 lpc1343fbd48 32 kb 8 kb device no 1 1 1 8 48 LQFP48 table 2. ordering option s for lpc1311/13/42/43 ?continued type number flash total sram usb power profiles uart rs-485 i 2 c/ fast+ ssp adc channels pins package
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 5 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 5. block diagram (1) lpc1342/43 only. (2) LQFP48 package only. (3) on lpc1313fbd48/01 only. (4) windowed watchdog timer (wwdt) on lpc1311/01 and lpc1313/01 only. fig 1. block diagram sram 4/8 kb arm cortex-m3 test/debug interface flash 8/16/32 kb usb device controller (1) i-code bus d-code bus system bus ahb to apb bridge high-speed gpio clock generation, power control, system functions xtalin xtalout reset clocks and controls swd usb phy (1) ssp0 10-bit adc uart 32-bit counter/timer 0 i 2 c-bus wdt/wwdt (4) ioconfig lpc1311/13/42/43 slave 002aae722 slave slave slave slave rom slave ahb-lite bus gpio ports pio0/1/2/3 ct32b0_mat[3:0] ad[7:0] ct32b0_cap0 sda scl rxd txd dtr, dsr (2) , cts, dcd (2) , ri (2) , rts system control 32-bit counter/timer 1 ct32b1_mat[3:0] ct32b1_cap0 16-bit counter/timer 1 ct16b1_mat[1:0] ct16b1_cap0 16-bit counter/timer 0 ct16b0_mat[2:0] ct16b0_cap0 usb pins sck0,ssel0 miso0, mosi0 ssp1 (3) sck1,ssel1 miso1, mosi0 clkout irc wdo por
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 6 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 6. pinning information 6.1 pinning fig 2. lpc1342/43 LQFP48 package lpc1342fbd48 lpc1343fbd48 pio2_6 pio3_0 pio2_0/dtr r/pio1_2/ad3/ct32b1_mat1 reset/pio0_0 r/pio1_1/ad2/ct32b1_mat0 pio0_1/clkout/ct32b0_mat2/usb_ftoggle r/pio1_0/ad1/ct32b1_cap0 v ss r/pio0_11/ad0/ct32b0_mat3 xtalin pio2_11/sck0 xtalout pio1_10/ad6/ct16b1_mat1 v dd swclk/pio0_10/sck0/ct16b0_mat2 pio1_8/ct16b1_cap0 pio0_9/mosi0/ct16b0_mat1/swo pio0_2/ssel0/ct16b0_cap0 pio0_8/miso0/ct16b0_mat0 pio2_7 pio2_2/dcd pio2_8 pio2_10 pio2_1/dsr pio3_3 pio0_3/usb_vbus pio1_7/txd/ct32b0_mat1 pio0_4/scl pio1_6/rxd/ct32b0_mat0 pio0_5/sda pio1_5/rts/ct32b0_cap0 pio1_9/ct16b1_mat0 v dd pio2_4 pio3_2 usb_dm pio1_11/ad7 usb_dp v ss pio2_5 pio1_4/ad5/ct32b1_mat3/wakeup pio0_6/usb_connect/sck swdio/pio1_3/ad4/ct32b1_mat2 pio0_7/cts pio2_9 pio2_3/ri pio3_1 002aae505 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 7 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller fig 3. lpc1342/43 hvqfn33 package 002aae516 lpc1342fhn33 lpc1343fhn33 transparent top view pio0_8/miso0/ct16b0_mat0 pio1_8/ct16b1_cap0 pio0_2/ssel0/ct16b0_cap0 pio0_9/mosi0/ct16b0_mat1/swo v dd swclk/pio0_10/sck0/ct16b0_mat2 xtalout pio1_10/ad6/ct16b1_mat1 xtalin r/pio0_11/ad0/ct32b0_mat3 pio0_1/clkout/ct32b0_mat2/usb_ftoggle r/pio1_0/ad1/ct32b1_cap0 reset/pio0_0 r/pio1_1/ad2/ct32b1_mat0 pio2_0/dtr r/pio1_2/ad3/ct32b1_mat1 pio0_3/usb_vbus pio0_4/scl pio0_5/sda pio1_9/ct16b1_mat0 usb_dm usb_dp pio0_6/usb_connect/sck0 pio0_7/cts pio1_7/txd/ct32b0_mat1 pio1_6/rxd/ct32b0_mat0 pio1_5/rts/ct32b0_cap0 v dd pio3_2 pio1_11/ad7 pio1_4/ad5/ct32b1_mat3/wakeup swdio/pio1_3/ad4/ct32b1_mat2 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area 33 v ss
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 8 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller (1) ssp1 or uart function on lpc1313fbd48/01 only. fig 4. lpc1313 LQFP48 package lpc1313fbd48 lpc1313fbd48/01 pio2_6 pio3_0 pio2_0/dtr/ssel1 (1) r/pio1_2/ad3/ct32b1_mat1 reset/pio0_0 r/pio1_1/ad2/ct32b1_mat0 pio0_1/clkout/ct32b0_mat2 r/pio1_0/ad1/ct32b1_cap0 v ss r/pio0_11/ad0/ct32b0_mat3 xtalin pio2_11/sck0 xtalout pio1_10/ad6/ct16b1_mat1 v dd swclk/pio0_10/sck0/ct16b0_mat2 pio1_8/ct16b1_cap0 pio0_9/mosi0/ct16b0_mat1/swo pio0_2/ssel0/ct16b0_cap0 pio0_8/miso0/ct16b0_mat0 pio2_7 pio2_2/dcd/miso1 (1) pio2_8 pio2_10 pio2_1/dsr/sck1 (1) pio3_3 pio0_3 pio1_7/txd/ct32b0_mat1 pio0_4/scl pio1_6/rxd/ct32b0_mat0 pio0_5/sda pio1_5/rts/ct32b0_cap0 pio1_9/ct16b1_mat0 v dd pio3_4 pio3_2 pio2_4 pio1_11/ad7 pio2_5 v ss pio3_5 pio1_4/ad5/ct32b1_mat3/wakeup pio0_6/sck0 swdio/pio1_3/ad4/ct32b1_mat2 pio0_7/cts pio2_9 pio2_3/ri/mosi1 (1) pio3_1 002aae513 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 9 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller fig 5. lpc1311/13 hvqfn33 package 002aae517 lpc1311fhn33 lpc1311fhn33/01 lpc1313fhn33 lpc1313fhn33/01 transparent top view pio0_8/miso0/ct16b0_mat0 pio1_8/ct16b1_cap0 pio0_2/ssel0/ct16b0_cap0 pio0_9/mosi0/ct16b0_mat1/swo v dd swclk/pio0_10/sck0/ct16b0_mat2 xtalout pio1_10/ad6/ct16b1_mat1 xtalin r/pio0_11/ad0/ct32b0_mat3 pio0_1/clkout/ct32b0_mat2 r/pio1_0/ad1/ct32b1_cap0 reset/pio0_0 r/pio1_1/ad2/ct32b1_mat0 pio2_0/dtr r/pio1_2/ad3/ct32b1_mat1 pio0_3 pio0_4/scl pio0_5/sda pio1_9/ct16b1_mat0 pio3_4 pio3_5 pio0_6/sck0 pio0_7/cts pio1_7/txd/ct32b0_mat1 pio1_6/rxd/ct32b0_mat0 pio1_5/rts/ct32b0_cap0 v dd pio3_2 pio1_11/ad7 pio1_4/ad5/ct32b1_mat3/wakeup swdio/pio1_3/ad4/ct32b1_mat2 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area 33 v ss
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 10 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 6.2 pin description table 3. lpc1313/42/43 LQFP48 pin description table symbol pin start logic input type reset state [1] description reset /pio0_0 3 [2] yes i i; pu reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. i/o - pio0_0 ? general purpose digital input/ output pin with 10 ns glitch filter. pio0_1/clkout/ ct32b0_mat2/ usb_ftoggle 4 [3] yes i/o i; pu pio0_1 ? general purpose digital input/output pin. a low level on this pin during reset starts the isp command handler or the usb device enumeration (usb on lpc1342/43 only, see description of pio0_3). o- clkout ? clockout pin. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. o- usb_ftoggle ? usb 1 ms start-of-frame signal (lpc1342/43 only). pio0_2/ssel0/ ct16b0_cap0 10 [3] yes i/o i; pu pio0_2 ? general purpose digital input/output pin. i/o - ssel0 ? slave select for ssp0. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_3/usb_vbus 14 [3] yes i/o i; pu pio0_3 ? general purpose digital inpu t/output pin. lpc1342/43 only: a low level on this pin during reset starts the isp command handler, a high level starts the usb device enumeration. i- usb_vbus ? monitors the presence of usb bus power (lpc1342/43 only). pio0_4/scl 15 [4] yes i/o i; ia pio0_4 ? general purpose digital inpu t/output pin (open-drain). i/o - scl ? i 2 c-bus clock input/output (open-drain). high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_5/sda 16 [4] yes i/o i; ia pio0_5 ? general purpose digital inpu t/output pin (open-drain). i/o - sda ? i 2 c-bus data input/output (open-drain). high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_6/ usb_connect / sck0 22 [3] yes i/o i; pu pio0_6 ? general purpose digital input/output pin. o- usb_connect ? signal used to switch an external 1.5 k resistor under software control. used with the softconnect usb feature (lpc1342/43 only). i/o - sck0 ? serial clock for ssp0. pio0_7/cts 23 [3] yes i/o i; pu pio0_7 ? general purpose digital inpu t/output pin (high-current output driver). i- cts ? clear to send input for uart. pio0_8/miso0/ ct16b0_mat0 27 [3] yes i/o i; pu pio0_8 ? general purpose digital input/output pin. i/o - miso0 ? master in slave out for ssp0. o- ct16b0_mat0 ? match output 0 for 16-bit timer 0.
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 11 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller pio0_9/mosi0/ ct16b0_mat1/ swo 28 [3] yes i/o i; pu pio0_9 ? general purpose digital input/output pin. i/o - mosi0 ? master out slave in for ssp0. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. o- swo ? serial wire trace output. swclk/pio0_10/ sck0/ct16b0_mat2 29 [3] yes i i; pu swclk ? serial wire clock. i/o - pio0_10 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for ssp0. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0. r/pio0_11/ ad0/ct32b0_mat3 32 [5] yes - i; pu r ? reserved. configure for an altern ate function in the ioconfig block. i/o - pio0_11 ? general purpose digital input/output pin. i- ad0 ? a/d converter, input 0. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. r/pio1_0/ ad1/ct32b1_cap0 33 [5] yes - i; pu r ? reserved. configure for an altern ate function in the ioconfig block. i/o - pio1_0 ? general purpose digital input/output pin. i- ad1 ? a/d converter, input 1. i- ct32b1_cap0 ? capture input 0 for 32-bit timer 1. r/pio1_1/ ad2/ct32b1_mat0 34 [5] yes - i; pu r ? reserved. configure for an altern ate function in the ioconfig block. i/o - pio1_1 ? general purpose digital input/output pin. i- ad2 ? a/d converter, input 2. o- ct32b1_mat0 ? match output 0 for 32-bit timer 1. r/pio1_2/ ad3/ct32b1_mat1 35 [5] yes - i; pu r ? reserved. configure for an altern ate function in the ioconfig block. i/o - pio1_2 ? general purpose digital input/output pin. i- ad3 ? a/d converter, input 3. o- ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio1_3/ ad4/ ct32b1_mat2 39 [5] yes i/o i; pu swdio ? serial wire debug input/output. i/o - pio1_3 ? general purpose digital input/output pin. i- ad4 ? a/d converter, input 4. o- ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_4/ad5/ ct32b1_mat3/ wakeup 40 [5] yes i/o i; pu pio1_4 ? general purpose digital input/output pin. i- ad5 ? a/d converter, input 5. o- ct32b1_mat3 ? match output 3 for 32-bit timer 1. i- wakeup ? deep power-down mode wake-up pin with 20 ns glitch filter. this pin must be pulled high externally to enter deep power-down mode and pulled low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. table 3. lpc1313/42/43 LQFP48 pin description table ?continued symbol pin start logic input type reset state [1] description
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 12 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller pio1_5/rts / ct32b0_cap0 45 [3] yes i/o i; pu pio1_5 ? general purpose digital input/output pin. o- rts ? request to send output for uart. i- ct32b0_cap0 ? capture input 0 for 32-bit timer 0. pio1_6/rxd/ ct32b0_mat0 46 [3] yes i/o i; pu pio1_6 ? general purpose digital input/output pin. i- rxd ? receiver input for uart. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio1_7/txd/ ct32b0_mat1 47 [3] yes i/o i; pu pio1_7 ? general purpose digital input/output pin. o- txd ? transmitter output for uart. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio1_8/ct16b1_cap0 9 [3] yes i/o i; pu pio1_8 ? general purpose digital input/output pin. i- ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio1_9/ct16b1_mat0 17 [3] yes i/o i; pu pio1_9 ? general purpose digital input/output pin. o- ct16b1_mat0 ? match output 0 for 16-bit timer 1. pio1_10/ad6/ ct16b1_mat1 30 [5] yes i/o i; pu pio1_10 ? general purpose digital input/output pin. i- ad6 ? a/d converter, input 6. o- ct16b1_mat1 ? match output 1 for 16-bit timer 1. pio1_11/ad7 42 [5] yes i/o i; pu pio1_11 ? general purpose digital input/output pin. i- ad7 ? a/d converter, input 7. pio2_0/dtr /ssel1 2 [3] yes i/o i; pu pio2_0 ? general purpose digital input/output pin. o- dtr ? data terminal ready output for uart. i/o - ssel1 ? slave select for ssp1 (lpc1313fbd48/01 only). pio2_1/dsr /sck1 13 [3] yes i/o i; pu pio2_1 ? general purpose digital input/output pin. i- dsr ? data set ready input for uart. i/o - sck1 ? serial clock for ssp1 (l pc1313fbd48/01 only). pio2_2/dcd /miso1 26 [3] yes i/o i; pu pio2_2 ? general purpose digital input/output pin. i- dcd ? data carrier detect input for uart. i/o - miso1 ? master in slave out for ssp1 (lpc1313fbd48/01 only). pio2_3/ri /mosi1 38 [3] yes i/o i; pu pio2_3 ? general purpose digital input/output pin. i- ri ? ring indicator input for uart. i/o - mosi1 ? master out slave in for ssp1 (lpc1313fbd48/01 only). pio2_4 18 [3] yes i/o i; pu pio2_4 ? general purpose digital in put/output pin (lpc1342/43 only). pio2_4 19 [3] yes i/o i; pu pio2_4 ? general purpose digital inpu t/output pin (lpc1313 only). pio2_5 21 [3] yes i/o i; pu pio2_5 ? general purpose digital in put/output pin (lpc1342/43 only). pio2_5 20 [3] yes i/o i; pu pio2_5 ? general purpose digital inpu t/output pin (lpc1313 only). pio2_6 1 [3] yes i/o i; pu pio2_6 ? general purpose digital input/output pin. pio2_7 11 [3] yes i/o i; pu pio2_7 ? general purpose digital input/output pin. pio2_8 12 [3] yes i/o i; pu pio2_8 ? general purpose digital input/output pin. pio2_9 24 [3] yes i/o i; pu pio2_9 ? general purpose digital input/output pin. table 3. lpc1313/42/43 LQFP48 pin description table ?continued symbol pin start logic input type reset state [1] description
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 13 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller [1] pin state at reset for default function: i = input; o = output; pu = internal pull-up enabled (for v dd = 3.3 v, pin is pulled up to 2.6 v for parts lpc1311/13/42/43 and pulled up to 3.3 v for parts lpc 1311/01 and lpc1313/01); ia = inactive, no pull-up/down enabled; f = floating; floating pins, if not used, should be ti ed to ground or power to minimize power consumption. [2] 5 v tolerant pad. see figure 37 for pad characteristics. reset functionality is not available in deep power-down mode. use the wakeup pin to reset the chip and wake up from deep power-down mo de. an external pull-up resistor is required on this pin for th e deep power-down mode. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis ( see figure 36 ). [4] i 2 c-bus pads compliant with the i 2 c-bus specification for i 2 c standard mode and i 2 c fast-mode plus. [5] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of the pad is disabled and the pin is not 5 v tolerant (see figure 36 ). [6] pad provides usb functions. it is designed in accordance with the usb specification, revision 2.0 (full-speed and low-speed mode only). this pad is not 5 v tolerant. [7] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. pio2_10 25 [3] yes i/o i; pu pio2_10 ? general purpose digital input/output pin. pio2_11/sck0 31 [3] yes i/o i; pu pio2_11 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for ssp0. pio3_0/dtr 36 [3] yes i/o i; pu pio3_0 ? general purpose digital input/output pin. o- dtr ? data terminal ready output for uart (lpc1311/01 and lpc1313/01 only). pio3_1/dsr 37 [3] yes i/o i; pu pio3_1 ? general purpose digital input/output pin. i- dsr ? data set ready input for uart (lpc1311/01 and lpc1313/01 only). pio3_2/dcd 43 [3] yes i/o i; pu pio3_2 ? general purpose digital input/output pin. i- dcd ? data carrier detect input for uart (lpc1311/01 and lpc1313/01 only). pio3_3/ri 48 [3] yes i/o i; pu pio3_3 ? general purpose digital input/output pin. i- ri ? ring indicator input for uart (lpc1311/01 and lpc1313/01 only). pio3_4 18 [3] no i/o i; pu pio3_4 ? general purpose digital inpu t/output pin (lpc1313 only). pio3_5 21 [3] no i/o i; pu pio3_5 ? general purpose digital inpu t/output pin (lpc1313 only). usb_dm 19 [6] no i/o f usb_dm ? usb bidirectional d ? line (lpc1342/43 only). usb_dp 20 [6] no i/o f usb_dp ? usb bidirectional d+ line (lpc1342/43 only). v dd 8; 44 - i - 3.3 v supply voltage to the internal regulator, the external rail, and the adc. also used as the adc reference voltage. xtalin 6 [7] - i - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 7 [7] - o - output from the oscillator amplifier. v ss 5; 41 - i - ground. table 3. lpc1313/42/43 LQFP48 pin description table ?continued symbol pin start logic input type reset state [1] description
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 14 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller table 4. lpc1311/13/42/43 hvqf n33 pin description table symbol pin start logic input type reset state [1] description reset /pio0_0 2 [2] yes i i; pu reset ? external reset input with 20 ns gl itch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. i/o - pio0_0 ? general purpose digital input/output pin with 10 ns glitch filter. pio0_1/clkout/ ct32b0_mat2/ usb_ftoggle 3 [3] yes i/o i; pu pio0_1 ? general purpose digital input/out put pin. a low level on this pin during reset starts the isp command handler or the usb device enumeration (usb on lpc1342/43 only, see description of pio0_3). o- clkout ? clock out pin. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. o- usb_ftoggle ? usb 1 ms start-of-frame signal (lpc1342/43 only). pio0_2/ssel0/ ct16b0_cap0 8 [3] yes i/o i; pu pio0_2 ? general purpose digital input/output pin. i/o - ssel0 ? slave select for ssp0. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_3/ usb_vbus 9 [3] yes i/o i; pu pio0_3 ? general purpose digital input/o utput pin. lpc1342/43 only: a low level on this pin during reset starts the isp command handler, a high level starts the usb device enumeration. i- usb_vbus ? monitors the presence of usb bus power (lpc1342/43 only). pio0_4/scl 10 [4] yes i/o i; ia pio0_4 ? general purpose digital input /output pin (open-drain). i/o - scl ? i 2 c-bus clock input/output (open-drain). high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_5/sda 11 [4] yes i/o i; ia pio0_5 ? general purpose digital input /output pin (open-drain). i/o - sda ? i 2 c-bus data input/output (open-dr ain). high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_6/ usb_connect / sck0 15 [3] yes i/o i; pu pio0_6 ? general purpose digital input/output pin. o- usb_connect ? signal used to switch an external 1.5 k resistor under software control. used with the softconnect usb feature (lpc1342/43 only). i/o - sck0 ? serial clock for ssp0. pio0_7/cts 16 [3] yes i/o i; pu pio0_7 ? general purpose digital input/o utput pin (high-current output driver). i- cts ? clear to send input for uart. pio0_8/miso0/ ct16b0_mat0 17 [3] yes i/o i; pu pio0_8 ? general purpose digital input/output pin. i/o - miso0 ? master in slave out for ssp0. o- ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_9/mosi0/ ct16b0_mat1/ swo 18 [3] yes i/o i; pu pio0_9 ? general purpose digital input/output pin. i/o - mosi0 ? master out slave in for ssp0. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. o- swo ? serial wire trace output.
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 15 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller swclk/pio0_10/ sck0/ ct16b0_mat2 19 [3] yes i i; pu swclk ? serial wire clock. i/o - pio0_10 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for ssp0. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0. r/pio0_11/ad0/ ct32b0_mat3 21 [5] yes - i; pu r ? reserved. configure for an alte rnate function in the ioconfig block. i/o - pio0_11 ? general purpose digital input/output pin. i- ad0 ? a/d converter, input 0. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. r/pio1_0/ad1/ ct32b1_cap0 22 [5] yes - i; pu r ? reserved. configure for an alte rnate function in the ioconfig block. i/o - pio1_0 ? general purpose digital input/output pin. i- ad1 ? a/d converter, input 1. i- ct32b1_cap0 ? capture input 0 for 32-bit timer 1. r/pio1_1/ad2/ ct32b1_mat0 23 [5] yes - i; pu r ? reserved. configure for an alte rnate function in the ioconfig block. i/o - pio1_1 ? general purpose digital input/output pin. i- ad2 ? a/d converter, input 2. o- ct32b1_mat0 ? match output 0 for 32-bit timer 1. r/pio1_2/ad3/ ct32b1_mat1 24 [5] yes - i; pu r ? reserved. configure for an alte rnate function in the ioconfig block. i/o - pio1_2 ? general purpose digital input/output pin. i- ad3 ? a/d converter, input 3. o- ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio1_3/ ad4/ ct32b1_mat2 25 [5] yes i/o i; pu swdio ? serial wire debug input/output. i/o - pio1_3 ? general purpose digital input/output pin. i- ad4 ? a/d converter, input 4. o- ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_4/ad5/ ct32b1_mat3/ wakeup 26 [5] yes i/o i; pu pio1_4 ? general purpose digital input/output pin. i- ad5 ? a/d converter, input 5. o- ct32b1_mat3 ? match output 3 for 32-bit timer 1. i- wakeup ? deep power-down mode wake-up pin with 20 ns glitch filter. this pin must be pulled high externally to enter deep power-down mode and pulled low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. pio1_5/rts / ct32b0_cap0 30 [3] yes i/o i; pu pio1_5 ? general purpose digital input/output pin. o- rts ? request to send output for uart. i- ct32b0_cap0 ? capture input 0 for 32-bit timer 0. pio1_6/rxd/ ct32b0_mat0 31 [3] yes i/o i; pu pio1_6 ? general purpose digital input/output pin. i- rxd ? receiver input for uart. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. table 4. lpc1311/13/42/43 hvqf n33 pin description table ?continued symbol pin start logic input type reset state [1] description
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 16 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller [1] pin state at reset for default function: i = input; o = output; pu = internal pull-up enabled (for v dd = 3.3 v, pin is pulled up to 2.6 v for parts lpc1311/13/42/43 and pulled up to 3.3 v for parts lpc1311/01 and lpc1313/01); ia = inactive, no pull-up/down enabled. f = floating; floating pins, if not used, should be ti ed to ground or power to minimize power consumption. [2] 5 v tolerant pad. see figure 37 for pad characteristics. reset functionality is not available in deep power-down mode. use the wakeup pin to reset the chip and wake up from deep power-down mo de. an external pull-up resistor is required on this pin for th e deep power-down mode. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis ( see figure 36 ). [4] i 2 c-bus pads compliant with the i 2 c-bus specification for i 2 c standard mode and i 2 c fast-mode plus. [5] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of the pad is disabled, and the pin is not 5 v tolerant (see figure 36 ). [6] pad provides usb functions. it is designed in accordance with the usb specification, revision 2.0 (full-speed and low-speed mode only). this pad is not 5 v tolerant. [7] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. pio1_7/txd/ ct32b0_mat1 32 [3] yes i/o i; pu pio1_7 ? general purpose digital input/output pin. o- txd ? transmitter output for uart. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio1_8/ ct16b1_cap0 7 [3] yes i/o i; pu pio1_8 ? general purpose digital input/output pin. i- ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio1_9/ ct16b1_mat0 12 [3] yes i/o i; pu pio1_9 ? general purpose digital input/output pin. o- ct16b1_mat0 ? match output 0 for 16-bit timer 1. pio1_10/ad6/ ct16b1_mat1 20 [5] yes i/o i; pu pio1_10 ? general purpose digital input/output pin. i- ad6 ? a/d converter, input 6. o- ct16b1_mat1 ? match output 1 for 16-bit timer 1. pio1_11/ad7 27 [5] yes i/o i; pu pio1_11 ? general purpose digital input/output pin. i- ad7 ? a/d converter, input 7. pio2_0/dtr 1 [3] yes i/o i; pu pio2_0 ? general purpose digital input/output pin. o- dtr ? data terminal ready output for uart. pio3_2 28 [3] yes i/o i; pu pio3_2 ? general purpose digital input/output pin. pio3_4 13 [3] no i/o i; pu pio3_4 ? general purpose digital input/output pin (lpc1311/13 only). pio3_5 14 [3] no i/o i; pu pio3_5 ? general purpose digital input/output pin (lpc1311/13 only). usb_dm 13 [6] no i/o f usb_dm ? usb bidirectional d ? line (lpc1342/43 only). usb_dp 14 [6] no i/o f usb_dp ? usb bidirectional d+ line (lpc1342/43 only). v dd 6; 29 - i - 3.3 v supply voltage to the internal regulator, the external rail, and the adc. also used as the adc reference voltage. xtalin 4 [7] - i - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 5 [7] - o - output from the oscillator amplifier. v ss 33 - - - thermal pad. connect to ground. table 4. lpc1311/13/42/43 hvqf n33 pin description table ?continued symbol pin start logic input type reset state [1] description
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 17 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 7. functional description 7.1 architectural overview the arm cortex-m3 includes th ree ahb-lite buses: the system bus, the i-code bus, and the d-code bus (see figure 1 ). the i-code and d-code core buses are faster than the system bus and are used similarly to tcm interfaces: one bus dedicated for instruction fetch (i-code) and one bus for data access (d-c ode). the use of two core buses allows for simultaneous operations if concurrent operations target different devices. 7.2 arm cortex-m3 processor the arm cortex-m3 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumptio n. the arm cortex-m3 offers many new features, including a thumb-2 instruction set, low interrupt latency, hardware multiply and divide, interruptible/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller, and multiple core buses capable of simultaneous accesses. pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. the arm cortex-m3 processor is described in detail in the cortex-m3 technical reference manual which is available on the official arm website. 7.3 on-chip flash program memory the lpc1311/13/42/43 contain 32 kb (lpc1313 and lpc1343), 16 kb (lpc1342), or 8 kb (lpc1311) of on-chip flash memory. 7.4 on-chip sram the lpc1311/13/42/43 contain a total of 8 kb (lpc1343 and lpc1313) or 4 kb (lpc1342 and lpc1311) on-chip static ram memory. 7.5 memory map the lpc1311/13/42/43 incorporate several distinct memory regions. figure 6 shows the overall map of the entire address space from the user program viewpoint following reset. the interrupt vector area supports address remapping. the ahb peripheral area is 2 mb in size and is divided to allow for up to 128 peripherals. the apb peripheral area is 512 kb in size and is divided to allow fo r up to 32 peripherals. each peripheral of either type is allocated 16 kb of space. this allows simplifying the address decoding for each peripheral.
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 18 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 7.6 nested vectored inte rrupt controller (nvic) the nested vectored in terrupt controller (nvic) is an integral part of the cortex-m3. the tight coupling to the cpu allows for low interr upt latency and efficient processing of late arriving interrupts. fig 6. lpc1311/13/42/43 memory map 0x5000 0000 0x5001 0000 0x5002 0000 0x5020 0000 ahb peripherals 16 - 127 reserved gpio pio1 4-7 0x5003 0000 0x5004 0000 gpio pio2 gpio pio3 8-11 12-15 gpio pio0 0-3 apb peripherals 0x4000 4000 0x4000 8000 0x4000 c000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4003 8000 0x4003 c000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 c000 0x4008 0000 0x4002 4000 0x4001 c000 0x4001 4000 0x4000 0000 wdt/wwdt 32-bit counter/timer 0 32-bit counter/timer 1 adc uart pmu i 2 c-bus 10 - 13 reserved reserved 19 - 21 reserved 23 - 31 reserved 0 1 2 3 4 5 6 7 8 9 16 15 14 17 18 reserved reserved 0x0000 0000 0 gb 0.5 gb 4 gb 1 gb 0x0000 4000 0x0000 2000 0x1000 2000 0x1000 1000 0x1fff 0000 0x1fff 4000 0x2000 0000 0x4000 0000 0x4008 0000 0x5000 0000 0x5020 0000 0xffff ffff reserved reserved reserved apb peripherals ahb peripherals 8 kb sram (lpc1313/1343) 0x1000 0000 4 kb sram (lpc1311/1342) lpc1311/13/42/43 16 kb on-chip flash (lpc1342) 8 kb on-chip flash (lpc1311) 0x0000 8000 32 kb on-chip flash (lpc1313/43) 16 kb boot rom 0x0000 0000 0x0000 0400 active interrupt vectors + 256 words i-code/d-code memory space 002aae723 reserved reserved ssp0 0x4005 8000 0x4005 c000 22 ssp1 (lpc1313fbd48/01) 16-bit counter/timer 1 16-bit counter/timer 0 usb (lpc1342/43 only) ioconfig system control flash controller 0xe000 0000 0xe010 0000 private peripheral bus
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 19 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 7.6.1 features ? controls system exceptions and peripheral interrupts. ? on the lpc1311/13/42/43, the nvic suppor ts up to 17 vector ed interrupts. in addition, up to 40 of the individual gpio inputs are nvic-vector capable. ? 8 programmable interrupt priority levels , with hardware priority level masking ? relocatable vector table. ? software interr upt generation. 7.6.2 interrupt sources each peripheral device has one interrupt line connected to the nvic but may have several interrupt flags. individual interrupt flags may also represent more than one interrupt source. any gpio pin (total of up to 42 pins) regardless of the selected function, can be programmed to generate an interrupt on a level, or rising edge or falling edge, or both. 7.7 ioconfig block the ioconfig block allows sele cted pins of the microcontroller to have more than one function. configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. activi ty of any enabled peripheral function that is not mapped to a related pin should be considered undefined. 7.8 fast general purpose parallel i/o device pins that are not connec ted to a specific peripheral function are controlled by the gpio registers. pins may be dynamically configured as inputs or outputs. multiple outputs can be set or cleared in one write operation. lpc1311/13/42/43 use acce lerated gpio functions: ? gpio block is a dedicated ahb peripheral so that the fastest possible i/o timing can be achieved. ? entire port value can be written in one instruction. additionally, any gpio pin (total of up to 42 pins) providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both. 7.8.1 features ? bit level port registers allow a single instruct ion to set or clear any number of bits in one write operation. ? direction control of individual bits. ? all i/o default to inputs with pull-up resist ors enabled after reset with the exception of the i 2 c-bus pins pio0_4 and pio0_5. ? pull-up/pull-down resistor configuration can be programmed through the ioconfig block for each gpio pin.
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 20 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller ? on the lpc1311/13/42/43, all gpio pins (except pio0_4 and pio0_5) are pulled up to 2.6 v (v dd = 3.3 v) if their pull-up resistor is enabled in the ioconfig block. ? on the lpc1311/01 and lpc1313/01, all gp io pins (except pio0_4 and pio0_5) are pulled up to 3.3 v (v dd = 3.3 v) if their pull-up resistor is enabled in the ioconfig block. 7.9 usb interface (lpc1342/43 only) the universal serial bu s (usb) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. the host controller allocates the usb bandwidth to attached devices through a token-based protocol. the bus supports hot-plugging and dynamic configuration of the de vices. all transactions are initiated by the host controller. the lpc1342/43 usb interface is a device controller with on-chip phy for device functions. 7.9.1 full-speed usb device controller the device controller enables 12 mbit/s data exchange with a usb host controller. it consists of a register interface, serial interface engine, and endpoint buffer memory. the serial interface engine decodes the usb data stream and writes data to the appropriate endpoint buffer. the status of a completed usb transfer or error condition is indicated via status registers. an interrupt is also generated if enabled. 7.9.1.1 features ? dedicated usb pll available. ? fully compliant with usb 2.0 specification (full speed) . ? supports 10 physical (5 logical) endpoints with up to 64 bytes buffer ram per endpoint (see table 5 ). ? supports control, bulk, isochronous, and interrupt endpoints. ? supports softconnect feature. ? double buffer implementation for bulk and isochronous endpoints. table 5. usb device endpoint configuration logical endpoint physical endpoint endpoint type direction packet size (byte) double buffer 0 0 control out 64 no 0 1 control in 64 no 1 2 interrupt/bulk out 64 no 1 3 interrupt/bulk in 64 no 2 4 interrupt/bulk out 64 no 2 5 interrupt/bulk in 64 no 3 6 interrupt/bulk out 64 yes 3 7 interrupt/bulk in 64 yes 4 8 isochronous out 512 yes 4 9 isochronous in 512 yes
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 21 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 7.10 uart the lpc1311/13/42/43 contains one uart. support for rs-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. the uart includes a fractional baud rate generator. standard baud rates such as 115200 bd can be achieved with any crystal frequency above 2 mhz. 7.10.1 features ? maximum uart data bit rate of 4.5 mbit/s. ? 16-byte receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator cove ring wide range of baud rates without a need for external crystals of particular values. ? fractional divider for baud rate control, auto baud capabilities and fifo control mechanism that enables software flow control implementation. ? support for rs-485/9-bit mode. ? support for modem control. 7.11 ssp serial i/o controller the lpc1311/13/42/43 contain one ssp cont roller. an additional ssp controller is available on the lpc1313fbd48/01 package. the ssp controller is capable of operation on a ssp, 4-wire ssi, or microwire bus. it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bus during a given data trans fer. the ssp supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. in practice, often only one of these data flows carries meaningful data. 7.11.1 features ? maximum ssp speed of 36 mbit/s (master) or 6 mbit/s (slave) ? compatible with motorola spi, 4-wire texas instruments ssi, and national semiconductor microwire buses ? synchronous serial communication ? master or slave operation ? 8-frame fifos for both transmit and receive ? 4-bit to 16-bit frame 7.12 i 2 c-bus serial i/o controller the lpc1311/13/42/43 contain one i 2 c-bus controller.
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 22 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller the i 2 c-bus is bidirectional for inter-ic control using only two wires: a serial clock line (scl) and a serial data line (sda). each de vice is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver) or a transmitter with the capability to both receive and send information (such as me mory). transmitters and/or receivers can operate in either master or sl ave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus and can be controlled by more than one bus master connected to it. 7.12.1 features ? the i 2 c-bus interface is a standard i 2 c-bus compliant interfac e with true open-drain pins. the i 2 c-bus interface also supports fast-mode plus with bit rates up to 1 mbit/s. ? easy to configure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can be used for test and diagnostic purposes. ? the i 2 c-bus controller supports multiple address recognition and a bus monitor mode. 7.13 10-bit adc the lpc1311/13/42/43 contains one adc. it is a single 10-bit successive approximation adc with eight channels. 7.13.1 features ? 10-bit successive approximation adc. ? input multiplexing among 8 pins. ? power-down mode. ? measurement range 0 v to v dd . ? 10-bit conversion time 2.44 s (up to 400 ksamples/s). ? burst conversion mode for single or multiple inputs. ? optional conversion on transition of input pin or timer match signal. ? individual result registers for each adc channel to reduce interrupt overhead.
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 23 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 7.14 general purpose externa l event counter/timers the lpc1311/13/42/43 includes two 32-bit counter/timers and two 16-bit counter/timers. the counter/timer is designed to count cycles of the system derived clock. it can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. each counter/timer also incl udes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.14.1 features ? a 32-bit/16-bit counter/timer with a programmable 32-bit/16-bit prescaler. ? counter or timer operation. ? one capture channel per timer, that can ta ke a snapshot of the timer value when an input signal transitions. a capture event may also generate an interrupt. ? four match registers per timer that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? up to four external outputs corresponding to match registers, with the following capabilities: ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match. 7.15 system tick timer the arm cortex-m3 includes a system tick timer (systic k) that is inte nded to generate a dedicated systick exception at a fixed time interval, norm ally set to 10 ms. 7.16 watchdog timer remark: the standard watchdog timer is ava ilable on parts lpc1311/13/42/43. the purpose of the watchdog is to reset t he microcontroller within a selectable time period. when enabled, the watchd og will generate a system reset if the user program fails to ?feed? (or reload) the watchdog with in a predetermined amount of time. 7.16.1 features ? internally resets chip if not period ically reloaded. ? debug mode. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect/incomplete feed sequence c auses reset/interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 24-bit timer with internal prescaler.
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 24 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller ? selectable time period from (t cy(wdclk) 256 4) to (t cy(wdclk) 2 24 4) in multiples of t cy(wdclk) 4. ? the watchdog clock (wdclk) source can be selected from the in ternal rc oscillator (irc), the watchdog oscillator, or the main clock. this gi ves a wide range of potential timing choices of watchdog operation under different power reduction conditions. it also provides the ability to run the wdt from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability. 7.17 windowed watc hdog timer (wwdt) remark: the windowed watchdog timer is available on parts lpc1311/01 and lpc1313/01. the purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.17.1 features ? internally resets chip if not periodically reloaded during the programmable time-out period. ? optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. ? optional warning interrupt can be generated at a programmable time prior to watchdog time-out. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect feed sequence causes reset or interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 24-bit timer with internal prescaler. ? selectable time period from (t cy(wdclk) 256 4) to (t cy(wdclk) 2 24 4) in multiples of t cy(wdclk) 4. ? the watchdog clock (wdclk) source can be selected from the irc or the dedicated watchdog oscillator (wdo). this gives a wide range of potential timing choices of watchdog operation under different power conditions. 7.18 clocking and power control 7.18.1 integrated oscillators the lpc1311/13/42/43 include three inde pendent oscillators. these are the system oscillator, the internal rc oscillator (irc), an d the watchdog oscillator. each oscillator can be used for more than one purpose as required in a particular application. following reset, the lpc1311/13 /42/43 will operate fr om the internal rc oscillator until switched by software. this a llows systems to operate without any external crystal and the bootloader code to operate at a known frequency. see figure 7 for an overview of the lpc1311/13/42/43 clock generation.
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 25 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 7.18.1.1 internal rc oscillator the irc may be used as the clock source for th e wdt, and/or as the clock that drives the system pll and subsequently the cpu. the nominal irc frequency is 12 mhz. the irc is trimmed to 1 % accuracy over the entire voltage and temperature range. the usb clock is available on lpc1342/43 only. ssp1 is available on lpc1313fbd48/01 only. fig 7. lpc1311/13/42/43 clocking generation block diagram system pll irc oscillator system oscillator system oscillator watchdog oscillator irc oscillator watchdog oscillator usb pll mainclksel (main clock select) syspllclksel (system pll clock select) usbpllclksel (usb clock select) system clock divider ahbclkctrl (ahb clock enable) ahb clock 0 (system) ahb clock 1 (rom) ahb clock 16 (ioconfig) ahbclkctrl ahbclkctrl ssp0/1 peripheral clock divider ssp0/1 uart peripheral clock divider uart systick timer clock divider wdt clock divider systick timer arm trace clock divider arm trace clock wdt wdtuen (wdt clock update enable) usb 48 mhz clock divider usb usbuen (usb clock update enable) watchdog oscillator irc oscillator system oscillator clkout pin clock divider clkout pin clkoutuen (clkout update enable) 002aae859 main clock system clock irc oscillator ahb clocks 2 to 15 (memories and peripherals) 14 2
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 26 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller upon power-up, any chip reset, or wake-up from deep power-down mode, the lpc1311/13/42/43 use the irc as the clock sour ce. software may later switch to one of the other available clock sources. 7.18.1.2 system oscillator the system oscillator can be used as the clock source for the cpu, with or without using the pll. on the lpc1342/43, the system oscillator must be used to provide the clock source to usb. the system oscillator operates at frequencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the system pll. 7.18.1.3 watchdog oscillator the watchdog oscillator can be used as a clock source that directly drives the cpu, the watchdog timer, or the clkout pin. the watchdog oscillator nominal frequency is programmable between 7.8 khz and 1.7 mhz. th e frequency spread over processing and temperature is 40 % (see also ta b l e 1 6 ). 7.18.2 system pll and usb pll the lpc1342/43 contain a system pll and a dedicated pll for generating the 48 mhz usb clock. the lpc131x contain the system pll only. the system and usb plls are identical. the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up to a high frequency with a curren t controlled oscillator (cco). the multiplier can be an integer value from 1 to 32. the cco operates in the range of 156 mhz to 320 mhz, so there is an additional divider in the loop to keep the cco within its frequency range while the pll is provid ing the desired output frequency. the output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. the pll output frequency must be lower than 100 mhz. since th e minimum output divider value is 2, it is insured that the pll output has a 50 % duty cycle. the pll is turned off and bypassed following a chip reset and may be enabled by software. the program must configure and activate the pll, wait for the pll to lock, and then connect to the pll as a clock source. the pll settling time is 100 s. 7.18.3 clock output the lpc1311/13/42/43 features a clock output function that routes the irc oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin. 7.18.4 wake-up process the lpc1311/13/42/43 begin operation at power-up and when awakened from deep power-down mode by using the 12 mhz irc o scillator as the clock source. this allows chip operation to resume quickly. if the ma in oscillator or the pll is needed by the application, software will need to enable these features an d wait for them to stabilize before they are used as a clock source.
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 27 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 7.18.5 power control the lpc1311/13/42/43 support a variety of power control features. there are three special modes of processor power reduction: sleep mode, deep-sleep mode, and deep power-down mode. the cpu clock rate may also be controlled as needed by changing clock sources, reconfiguring pll values, and/or altering the cpu clock divider value. this allows a trade-off of power versus processing speed based on application requirements. in addition, a register is pr ovided for shutting down the cl ocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required fo r the application. selected peripherals have their own clock divider which prov ides even better power control. 7.18.5.1 power profiles (lpc1300l ser ies, lpc1311/01 and lpc1313/01 only) the power consumption in active and sleep modes can be optimized for the application through simple calls to the power profile. the power configuration routine configures the lpc1311/01 and the lpc1313/01 for one of the following power modes: ? default mode corresponding to power configuration after reset. ? cpu performance mode co rresponding to optimize d processing capability. ? efficiency mode corresponding to optimize d balance of current consumption and cpu performance. ? low-current mode corresponding to lowest power consumption. in addition, the power profile includes routines to select the optimal pll settings for a given system clock and pll input clock. 7.18.5.2 sleep mode when sleep mode is entered, the clock to the core is stopped. resumption from the sleep mode does not need any special sequence but re-enabling the clock to the arm core. in sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue opera tion during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.18.5.3 deep-sleep mode in deep-sleep mode, the chip is in sleep mode, and in addition all analog blocks are shut down. as an exception, the user has the opt ion to keep the watchdog oscillator and the bod circuit running for self-timed wake-up and bod protection. deep-sleep mode allows for additional power savings. up to 40 pins total can serve as external wake-up pins to the start logic to wake up the chip from deep-sleep mode (see section 7.19.1 ). unless the watchdog oscillator is selected to run in deep-s leep mode, the clock source should be switched to irc before entering deep-sleep mode, because the irc can be switched on and off glitch-free.
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 28 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 7.18.5.4 deep power-down mode in deep power-down mode, power is shut off to the entire chip with the exception of the wakeup pin. the lpc131 1/13/42/43 can wake up from deep po wer-down mode via the wakeup pin. a low-going pulse as short as 50 ns wakes up the part from deep power-down mode. when entering deep power-down mode, an external pull-up resistor is required on the wakeup pin to hold it high. the reset pin must also be held high to prevent it from floating while in deep power-down mode. 7.19 system control 7.19.1 start logic the start logic connects external pins to corresponding interrupts in the nvic. each pin shown in ta b l e 3 and table 4 as input to the start logic has an individual interrupt in the nvic interrupt vector table. the start logic pi ns can serve as external interrupt pins when the chip is running. in addition, an input signal on the start logic pins can wake up the chip from deep-sleep mode when all clocks are shut down. the start logic must be configured in the system configuration block and in the nvic before being used. 7.19.2 reset reset has four sour ces on the lpc1311/ 13/42/43: the reset pin, the watchdog reset, power-on reset (por), and the brown-out detection (bod) circuit. the reset pin is a schmitt trigger input pin. assertion of chip re set by any source, once the operating voltage attains a usable level, starts the irc and initializes the flash controller. when the internal reset is removed, the proces sor begins executing at address 0, which is initially the reset vector mapped from the boot bl ock. at that point, all of the processor and peripheral registers have been initialized to predetermined values. 7.19.3 brownout detection the lpc1311/13/42/43 includes four levels for monitoring the voltage on the v dd pin. if this voltage falls below one of the four select ed levels, the bod asserts an interrupt signal to the nvic. this signal can be enabled for inte rrupt in the interrupt enable register in the nvic in order to cause a cpu in terrupt; if not, software can monitor the signal by reading a dedicated status register. an additional threshold level can be selected to cause a forced reset of the chip. 7.19.4 code security (code read protection - crp) this feature of the lpc1311/13/42/43 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the serial wire debugger (swd) and in-system programming (isp) can be restricted. when needed, crp is invoked by programming a specific pattern into a dedicated flash location. in-application programming (iap) commands are not affected by the crp. in addition, isp entry via the pio0_1 pin ca n be disabled without enabling crp (no_isp mode). for details see the lpc13xx user manual .
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 29 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller there are three levels of code read protection: 1. crp1 disables access to chip via the swd and allows partial flash update (excluding flash sector 0) using a limited set of t he isp commands. this mode is useful when crp is required and flash field updates are needed but all sectors can not be erased. 2. crp2 disables access to chip via the swd and only allows full flash erase and update using a reduced set of the isp commands. 3. running an applicatio n with level crp3 selected fully disables any access to chip via the swd pins and the isp. this mode effect ively disables isp override using pio0_1 pin, too. it is up to the user?s applicat ion to provide (if needed) flash update mechanism using iap calls or call reinvoke isp command to enable flash update via uart. 7.19.5 boot loader the boot loader controls initial operation after reset and also provides the means to program the flash memory. this could be init ial programming of a blank device, erasure and re-programming of a previously programmed device, or programming of the flash memory by the application program in a running system. the boot loader code is executed every time the part is reset or powered up. the loader can either execute the isp command handler or the user application code, or, on the lpc1342/43, it can program the flash image via an attached msc device through usb (windows operating system only). a low leve l during reset applied to the pio0_1 pin is considered as an external hardware request to start the isp command handler or the usb device enumeration. the stat e of pio0_3 determines whether the uart or usb interface will be used (lpc1342/43 only). 7.19.6 apb interface the apb peripherals are located on one apb bus. 7.19.7 ahb-lite the ahb-lite connects the instruction (i-code) and data (d-code) cpu buses of the arm cortex-m3 to the flash memory, the ma in static ram, and the boot rom. 7.19.8 external interrupt inputs all gpio pins can be level or edge sensitive interrupt inputs. in addition, start logic inputs serve as external interrupts (see section 7.19.1 ). 7.19.9 memory mapping control the cortex-m3 incorporates a me chanism that allows remapping the interrupt vector table to alternate locations in the memory map. th is is controlled via the vector table offset register contained in the nvic. caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device.
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 30 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller the vector table may be located anywhere within the bottom 1 gb of cortex-m3 address space. the vector table must be located on a 256 word boundary. 7.20 emulation and debugging debug functions are integrated into the arm cortex-m3. serial wire debug is supported.
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 31 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 8. limiting values [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. [2] including voltage on outputs in 3-state mode. [3] the maximum non-operating storage temperature is different t han the temperature for required shelf life which should be dete rmined based on required shelf lifetime. please refer to the jedec specification j-std-033b.1 for further details. [4] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k series resistor. table 6. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd supply voltage (core and external rail) 2.0 3.6 v v i input voltage 5 v tolerant i/o pins; only valid when the v dd supply voltage is present [2] ? 0.5 +5.5 v i dd supply current per supply pin - 100 ma i ss ground current per ground pin - 100 ma i latch i/o latch-up current ? (0.5v dd ) < v i < (1.5v dd ); t j < 125 c -100ma t stg storage temperat ure non-operating [3] ? 65 +150 c t j(max) maximum junction temperature - 150 c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1.5w v esd electrostatic discharge voltage human body model; all pins [4] ? 6500 +6500 v
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 32 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 9. static characteristics table 7. static characteristics t amb = ? 40 c to +85 c, unless otherwise specified. symbol parameter conditions min typ [1] max unit v dd supply voltage (core and external rail) [2] 2.0 3.3 3.6 v lpc1300 series (lpc1311/13/42/43) power consumption i dd supply current active mode; v dd =3.3v; t amb =25 c; code while(1){} executed from flash; system clock = 12 mhz [3] [4] [5] [6] [7] -4-ma system clock = 72 mhz [4] [5] [6] [8] [7] -17-ma sleep mode; v dd = 3.3 v; t amb =25 c; system clock = 12 mhz [3] [4] [5] [6] [7] -2-ma deep-sleep mode; v dd = 3.3 v; t amb =25 c [4] [9] [7] -30- a deep power-down mode; v dd =3.3v; t amb =25 c [10] - 220 - na lpc1300l series (lpc1311/01, lpc1313/01) power consumption in low-current mode [11] i dd supply current active mode; v dd =3.3v; t amb =25 c; code while(1){} executed from flash; system clock = 12 mhz [3] [4] [5] [6] [7] -2-ma system clock = 72 mhz [4] [5] [6] [8] [7] -13-ma sleep mode; v dd = 3.3 v; t amb =25 c; system clock = 12 mhz [3] [4] [5] [6] [7] -1-ma deep-sleep mode; v dd = 3.3 v; t amb =25 c [4] [9] [7] -2- a deep power-down mode; v dd =3.3v; t amb =25 c [10] - 220 - na standard port pins and reset pin; see figure 21 , figure 22 , figure 23 , figure 24 i il low-level input current v i = 0 v; on-chip pull-up resistor disabled -0.510na i ih high-level input current v i =v dd ; on-chip pull-down resistor disabled -0.510na i oz off-state output current v o =0v; v o =v dd ; on-chip pull-up/down resistors disabled -0.510na v i input voltage pin configured to provide a digital function [12] [13] [14] 0- 5.0v
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 33 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller v o output voltage output active 0 - v dd v v ih high-level input voltage 0.7v dd --v v il low-level input voltage - - 0.3v dd v v hys hysteresis voltage 0.4 - - v v oh high-level output voltage 2.5 v v dd 3.6 v; i oh = ? 4 ma v dd ? 0.4--v 2.0 v v dd < 2.5 v; i oh = ? 3 ma v dd ? 0.4--v v ol low-level output voltage 2.5 v v dd 3.6 v; i ol =4 ma --0.4v 2.0 v v dd < 2.5 v; i ol =3 ma --0.4v i oh high-level output current 2.5 v v dd 3.6 v; v oh =v dd ? 0.4 v ? 4--ma 2.0 v v dd < 2.5 v; v oh =v dd ? 0.4 v ? 3--ma i ol low-level output current 2.5 v v dd 3.6 v; v ol =0.4v 4--ma 2.0 v v dd < 2.5 v; v ol =0.4v 3--ma i ohs high-level short-circuit output current v oh =0v [15] --? 45 ma i ols low-level short-circuit output current v ol =v dd [15] --50ma i pd pull-down current v i =5v 1050150 a i pu pull-up current v i =0v ? 15 ? 50 ? 85 a v dd lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 34 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller i oh high-level output current 2.5 v v dd 3.6 v; v oh =v dd ? 0.4 v 20--ma 2.0 v v dd < 2.5 v; v oh =v dd ? 0.4 v; 12--ma i ol low-level output current 2.5 v v dd 3.6 v; v ol =0.4v 4--ma 2.0 v v dd < 2.5 v; v ol =0.4v 3--ma i pd pull-down current v i =5v 1050150 a i pu pull-up current v i =0v ? 15 ? 50 ? 85 a v dd lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 35 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 c), nominal supply voltages. [2] for lpc1342 and lpc1343 only: for usb operation 3.0 v v dd 3.6 v. guaranteed by design. [3] irc enabled; system oscillator disabled; system pll disabled. [4] i dd measurements were performed with all pins configured as gpio outputs driven low and pull-up resistors disabled. [5] bod disabled. [6] all peripherals disabled in the sysahbclkctrl register. peri pheral clocks to uart, ssp, trace clock, and systick timer disab led in the syscon block. [7] for lpc1342/43: usb_dp and usb_dm pulled low externally. [8] irc disabled; system oscill ator enabled; system pll enabled. [9] all oscillators and analog blocks turned off in the pdsleepcfg register; pdsleepcfg = 0x0000 0fff. [10] wakeup pin pulled high externally. an exte rnal pull-up resistor is required on the reset pin for the deep power-down mode. [11] low-current mode pwr_low_current selected when runni ng the set_power routine in the power profiles. [12] including voltage on outputs in 3-state mode. [13] v dd supply voltage must be present. [14] 3-state outputs go into 3-state mode in deep power-down mode. [15] allowed as long as the current limit does not exceed the maximum current allowed by the device. [16] to v ss . [17] 3.0 v v dd 3.6 v. [18] includes external resistors of 33 ? 1 % on usb_dp and usb_dm. [1] the adc is monotonic, there are no missing codes. [2] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 8 . v oh high-level output voltage driven; for low-/full-speed; r l of 15 k to gnd [17] 2.8 - 3.5 v c trans transceiver capacitance pin to gnd [17] --20pf z drv driver output impedance for driver which is not high-speed capable with 33 series resistor; steady state drive [18] [17] 36 - 44.1 table 7. static characteristics ?continued t amb = ? 40 c to +85 c, unless otherwise specified. symbol parameter conditions min typ [1] max unit table 8. adc static characteristics t amb = ? 40 c to +85 c unless otherwise specified; adc frequency 4.5 mhz, v dd = 2.5 v to 3.6 v. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dd v c ia analog input capacitance - - 1 pf e d differential linearity error [1] [2] -- 1lsb e l(adj) integral non-linearity [3] -- 1.5 lsb e o offset error [4] -- 3.5 lsb e g gain error [5] --0 . 6% e t absolute error [6] -- 4lsb r vsi voltage source interface resistance --40k r i input resistance [7] [8] --2 . 5m
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 36 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller [3] the integral non-linearity (e l(adj) ) is the peak difference between the center of the st eps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 8 . [4] the offset error (e o ) is the absolute difference between the straight line which fits the actual cu rve and the straight line which fits the ideal curve. see figure 8 . [5] the gain error (e g ) is the relative difference in percent between the straight line fitting the actual transfe r curve after removing offset error, and the straight line which fits the ideal transfer curve. see figure 8 . [6] the absolute error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 8 . [7] t amb = 25 c; maximum sampling frequency f s = 400 ksamples/s and analog input capacitance c ia = 1 pf. [8] input resistance r i depends on the sampling frequency f s : r i = 1 / (f s c ia ).
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 37 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 8. adc characteristics 002aaf426 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dd ? v ss 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 38 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 9.1 bod static character istics for lpc1300 series remark: applies to parts lpc1311/13/42/43 and all their packages. [1] interrupt levels are selected by writing the le vel value to the bod control register bodctrl, see lpc13xx user manual . table 9. bod static characteristics [1] t amb =25 c. symbol parameter conditions min typ max unit v th threshold voltage interrupt level 0 assertion - 1.69 - v de-assertion - 1.84 - v interrupt level 1 assertion - 2.29 - v de-assertion - 2.44 - v interrupt level 2 assertion - 2.59 - v de-assertion - 2.74 - v interrupt level 3 assertion - 2.87 - v de-assertion - 2.98 - v reset level 0 assertion - 1.49 - v de-assertion - 1.64 - v
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 39 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 9.2 bod static characteristics for lpc1300l series (lpc1311/01 and lpc1313/01) remark: applies to parts lpc1311/01 and lpc1313/01 and all packages. [1] interrupt levels are selected by writing the le vel value to the bod control register bodctrl, see lpc13xx user manual . 9.3 power consumpti on for lpc1300 series remark: applies to parts lpc1311/13/42/43 and all their packages. power measurements in active, sleep, and deep-sleep modes were performed under the following conditions (see lpc13xx user manual ): ? configure all pins as gpio with pull-up resistor disabled in the ioconfig block. ? configure gpio pins as outputs using the gpiondir registers. ? write 0 to all gpiondata registers to drive the outputs low. table 10. bod static characteristics [1] t amb =25 c. symbol parameter conditions min typ max unit v th threshold voltage interrupt level 0 assertion - 1.65 - v de-assertion - 1.80 - v interrupt level 1 assertion - 2.22 - v de-assertion - 2.35 - v interrupt level 2 assertion - 2.52 - v de-assertion - 2.66 - v interrupt level 3 assertion - 2.80 - v de-assertion - 2.90 - v reset level 0 assertion - 1.46 - v de-assertion - 1.63 - v reset level 1 assertion - 2.06 - v de-assertion - 2.15 - v reset level 2 assertion - 2.35 - v de-assertion - 2.43 - v reset level 3 assertion - 2.63 - v de-assertion - 2.71 - v
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 40 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller conditions: t amb = 25 c; active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; system oscillator and system pll enabled; irc, bod disabled; all peripherals disabled in the sysahbclkct rl register (sysahbclkctrl = 0x1f); all peripheral clocks disabled; usb_dp and u sb_dm pulled low externally (lpc1342/43). fig 9. typical supply current versus regulator supply voltage v dd in active mode (lpc1311/13/42/43) conditions: v dd = 3.3 v; active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; system oscillator and system pll enab led; irc, bod disabled; all peripherals disabled in the sysahbclkctrl regist er (sysahbclkctrl = 0x1f); all peripheral clocks disabled; usb_dp and usb_dm pulled low externally (lpc1342/43). fig 10. typical supply current versus temper ature in active mode (lpc1311/13/42/43) v dd (v) 2.0 3.6 3.2 2.8 2.4 002aae993 9 12 6 15 18 i dd (ma) 3 24 mhz 48 mhz 12 mhz 36 mhz 72 mhz 002aae994 temperature ( c) ?40 85 35 10 60 ?15 6 15 12 9 18 i dd (ma) 3 24 mhz 12 mhz 36 mhz 72 mhz 48 mhz
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 41 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller conditions: v dd = 3.3 v; sleep mode entered from flash; in ternal pull-up resistors disabled; system oscillator and system pll enabled; irc, bo d disabled; all peripherals disabled in the sysahbclkctrl register (sysahbclk ctrl = 0x1f); all peripheral clocks disabled; usb_dp and usb_dm pulled low externally (lpc1342/43). fig 11. typical supply current versus temper ature in sleep mode (lpc1311/13/42/43) conditions: bod disabled; all oscillators and analog blocks turned off in the pdsleepcfg register; pdsleepcfg = 0x0000 0fff; usb_ dp and usb_dm pulled low externally (lpc1342/43). fig 12. typical supply current versus temper ature in deep-sleep mode (analog blocks disabled; lpc1311/13/42/43) 002aae995 temperature ( c) ?40 85 35 10 60 ?15 2 8 6 4 10 i dd (ma) 0 12 mhz 36 mhz 72 mhz 48 mhz 24 mhz 002aae998 temperature ( c) ?40 85 35 10 60 ?15 20 60 40 80 i dd (a) 0 v dd = 3.6 v 3.3 v 2.0 v
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 42 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 9.4 power consumption for lp c1300l series (lpc1311/01 and lpc1313/01) remark: applies to parts lpc1311/01 and lpc1313/01 and all their packages. power measurements in active, sleep, and deep-sleep modes were performed under the following conditions (see lpc13xx user manual ): ? configure all pins as gpio with pull-up resistor disabled in the ioconfig block. ? configure gpio pins as outputs using the gpiondir registers. ? write 0 to all gpiondata registers to drive the outputs low. fig 13. typical supply current versus temperature in deep power-down mode (lpc1311/13/42/43) 002aae996 0.4 0.6 1.2 i dd (a) 0 temperature ( c) ?40 85 35 10 60 ?15 vdd = 3.6 v 3.3 v 2.0 v
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 43 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller conditions: t amb = 25 c; active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; system oscillator and system pll enabled; irc, bod disabled; all peripherals disabled in the sysahbclkct rl register (sysahbclkctrl = 0x1f); all peripheral clocks disabled; low-current mode. fig 14. typical supply current versus regulator supply voltage v dd in active mode (lpc1311/01 and lpc1313/01) conditions: v dd = 3.3 v; active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; system oscillator and system pll enab led; irc, bod disabled; all peripherals disabled in the sysahbclkctrl regist er (sysahbclkctrl = 0x1f); all peripheral clocks disabled; low-current mode. fig 15. typical supply current versus temper ature in active mode (lpc1311/01 and lpc1313/01) v dd (v) 2.0 3.6 3.2 2.8 2.4 002aag235 8 4 12 16 i dd (ma) 0 12 mhz 24 mhz 36 mhz 48 mhz 72 mhz 002aag236 temperature (c) ?40 85 35 10 60 ?15 4 12 8 16 i dd (ma) 0 12 mhz 24 mhz 36 mhz 48 mhz 72 mhz
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 44 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller conditions: v dd = 3.3 v; sleep mode entered from flash; in ternal pull-up resistors disabled; system oscillator and system pll enabled; irc, bo d disabled; all peripherals disabled in the sysahbclkctrl register (sysahbclkctrl = 0x1f); all peripheral clocks disabled; low-current mode. fig 16. typical supply current versus temp erature in sleep mode (lpc1311/01 and lpc1313/01) conditions: bod disabled; all oscillators and analog blocks turned off in the pdsleepcfg register; pdsleepcfg = 0x0000 0fff. fig 17. typical supply current versus temper ature in deep-sleep mode (analog blocks disabled, lpc1311/ 01 and lpc1313/01) 002aag237 temperature (c) ?40 85 35 10 60 ?15 2 6 4 8 i dd (ma) 0 12 mhz 24 mhz 36 mhz 48 mhz 72 mhz 002aag238 temperature (c) ?40 85 35 10 60 ?15 2 6 4 8 i dd (a) 0 vdd = 2.0 v 3.3 v 3.6 v
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 45 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 9.5 peripheral power consumption the supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disa bled in the sysahbclkcfg or pdruncfg (for analog blocks) re gisters. all other blocks are disabled in both registers and no code is executed. measured on a typical sample at t amb =25 c. unless noted otherwise, the system oscillator and pll are running in both measurements. the supply currents are shown for system clock frequencies of 12 mhz, 48 mhz, and 72 mhz. fig 18. typical supply current versus temperature in deep power-down mode (lpc1311/01 and lpc1313/01) 002aag239 0.2 0.4 0.6 i dd (a) 0 temperature (c) ?40 85 35 10 60 ?15 vdd = 3.6 v 3.3 v 2.0 v table 11. power consumption for individual analog and digital blocks peripheral typical supply current in ma notes n/a 12 mhz 48 mhz 72 mhz irc 0.23 - - - system oscillator running; pll off; independent of main clock frequency. system oscillator at 12 mhz 0.23 - - - irc running; pll off; independent of main clock frequency. watchdog oscillator at 500 khz/2 0.002 - - - system oscillator running; pll off; independent of main clock frequency. bod 0.045 - - - independent of main clock frequency. main or usb pll - 0.26 0.34 0.48 - adc - 0.07 0.25 0.37 - clkout - 0.14 0.56 0.82 main clock divided by 4 in the clkoutdiv register. ct16b0 - 0.01 0.05 0.08 - ct16b1 - 0.01 0.04 0.06 - ct32b0 - 0.01 0.05 0.07 - ct32b1 - 0.01 0.04 0.06 -
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 46 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 9.6 electrical pi n characteristics gpio - 0.21 0.80 1.17 gpio pins configured as outputs and set to low. direction and pin state are maintained if the gpio is disabled in the sysahbclkcfg register. ioconfig - 0.00 0.02 0.02 - i2c - 0.03 0.12 0.17 - rom - 0.04 0.15 0.22 - ssp0 - 0.11 0.41 0.60 - ssp1 - 0.11 0.41 0.60 on lpc1313fbd48/01 only. uart - 0.20 0.76 1.11 - wdt - 0.01 0.05 0.08 main clock select ed as clock source for the wdt. usb - - 3.91 - main clock selected as clock source for the usb. usb_dp and usb_dm pulled low externally. usb - 1.84 4.19 5.71 dedicated usb pll selected as clock source for the usb. usb_dp and usb_dm pulled low externally. table 11. power consumption for individual analog and digital blocks ?continued peripheral typical supply current in ma notes n/a 12 mhz 48 mhz 72 mhz conditions: v dd = 3.3 v; on pin pio0_7. fig 19. high-drive output: typical high-level output voltage v oh versus high-level output current i oh . i oh (ma) 0 60 40 20 10 50 30 002aae990 2.8 2.4 3.2 3.6 v oh (v) 2 t = 85 c 25 c ?40 c
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 47 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller conditions: v dd = 3.3 v; on pins pio0_4 and pio0_5. fig 20. i 2 c-bus pins (high current sink): typical low-level output current i ol versus low-level output voltage v ol conditions: v dd = 3.3 v; standard port pins and pio0_7. fig 21. typical low-l evel output current i ol versus low-level output voltage v ol v ol (v) 0 0.6 0.4 0.2 002aaf019 20 40 60 i ol (ma) 0 t = 85 c 25 c ?40 c v ol (v) 0 0.6 0.4 0.2 002aae991 5 10 15 i ol (ma) 0 t = 85 c 25 c ?40 c
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 48 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller conditions: v dd = 3.3 v; standard port pins. fig 22. typical high-level output voltage v oh versus high-level output source current i oh conditions: v dd = 3.3 v; standard port pins. fig 23. typical pull-up current i pu versus input voltage v i i oh (ma) 0 24 16 8 002aae992 2.8 2.4 3.2 3.6 v oh (v) 2 t = 85 c 25 c ?40 c v i (v) 0 5 4 23 1 002aae988 ?30 ?50 ?10 10 i pu (a) ?70 t = 85 c 25 c ?40 c
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 49 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller conditions: v dd = 3.3 v; standard port pins. fig 24. typical pull-down current i pd versus input voltage v i v i (v) 0 5 4 23 1 002aae989 40 20 60 80 i pd (a) 0 t = 85 c 25 c ?40 c
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 50 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 10. dynamic characteristics 10.1 power-up ramp conditions [1] see figure 25 . [2] the wait time specifies the time the power supply must be at levels below 400 mv before ramping up. 10.2 flash memory [1] number of program/erase cycles. [2] programming times are given for writing 256 bytes from ram to t he flash. data must be written to the flash in blocks of 256 bytes. table 12. power-up characteristics t amb = ? 40 c to +85 c. symbol parameter conditions min typ max unit t r rise time at t = t 1 : 0 < v i 400 mv [1] 0- 500 ms t wait wait time [1] [2] 12 - - s v i input voltage at t = t 1 on pin v dd 0 - 400 mv condition: 0 < v i 400 mv at start of power-up (t = t 1 ) fig 25. power-up ramp v dd 0 400 mv t r t wait t = t 1 002aag001 table 13. flash characteristics t amb = ? 40 c to +85 c, unless otherwise specified. symbol parameter conditions min typ max unit n endu endurance [1] 10000 100000 - cycles t ret retention time powered 10 - - years unpowered 20 - - years t er erase time sector or multiple consecutive sectors 95 100 105 ms t prog programming time [2] 0.95 1 1.05 ms
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 51 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 10.3 external clock [1] parameters are valid over operating tem perature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 c), nominal supply voltages. table 14. dynamic charact eristic: external clock t amb = ? 40 c to +85 c; v dd over specified ranges. [1] symbol parameter conditions min typ [2] max unit f osc oscillator frequency 1 - 25 mhz t cy(clk) clock cycle time 40 - 1000 ns t chcx clock high time t cy(clk) 0.4 - - ns t clcx clock low time t cy(clk) 0.4 - - ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns fig 26. external clock timing (wit h an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 52 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 10.4 internal oscillators [1] parameters are valid over operating tem perature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 c), nominal supply voltages. [1] typical ratings are not guaranteed. the va lues listed are at nominal supply voltages. [2] the typical frequency spread over processing and temperature (t amb = ?40 c to +85 c) is 40 %. [3] see the lpc13xx user manual. table 15. dynamic characteristics: irc t amb = ? 40 c to +85 c; 2.7 v v dd 3.6 v [1] . symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency - 11.88 12 12.12 mhz conditions: frequency values are typical values. 12 mhz 1 % accuracy is guaranteed for 2.7 v v dd 3.6 v and t amb = ?40 c to +85 c. variations between parts may cause the irc to fall outside the 12 mhz 1 % accuracy specification for voltages below 2.7 v. fig 27. internal rc oscillator frequency f versus temperature temperature ( c) ?40 85 35 10 60 ?15 002aae987 11.95 12.05 12.15 f (mhz) 11.85 v dd = 3.6 v 3.3 v 3.0 v 2.7 v 2.4 v 2.0 v table 16. dynamic characteristics: watchdog oscillator symbol parameter conditions min typ [1] max unit f osc(int) internal oscillator frequency divsel = 0x1f, freqsel = 0x1 in the wdtoscctrl register; [2] [3] -7.8 - khz divsel = 0x00, freqsel = 0xf in the wdtoscctrl register [2] [3] - 1700 - khz
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 53 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 10.5 i/o pins [1] applies to standard port pins and reset pin. 10.6 i 2 c-bus [1] see the i 2 c-bus specification um10204 for details. [2] parameters are valid over operating tem perature range unless otherwise specified. [3] t hd;dat is the data hold time that is measured from the falling edge of scl; applies to data in transmission and the acknowledge. [4] a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. [5] c b = total capacitance of one bus line in pf. [6] the maximum t f for the sda and scl bus lines is s pecified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection re sistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [7] in fast-mode plus, fall time is specified the same for bot h output stage and bus timing. if se ries resistors are used, desig ners should allow for this when c onsidering bus timing. table 17. dynamic characteristics: i/o pins [1] t amb = ? 40 c to +85 c; 3.0 v v dd 3.6 v. symbol parameter conditions min typ max unit t r rise time pin configured as output 3.0 - 5.0 ns t f fall time pin configured as output 2.5 - 5.0 ns table 18. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 c to +85 c. [2] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz fast-mode plus 0 1 mhz t f fall time [4] [5] [6] [7] of both sda and scl signals standard-mode -300ns fast-mode 20 + 0.1 c b 300 ns fast-mode plus - 120 ns t low low period of the scl clock standard-mode 4.7 - s fast-mode 1.3 - s fast-mode plus 0.5 - s t high high period of the scl clock standard-mode 4.0 - s fast-mode 0.6 - s fast-mode plus 0.26 - s t hd;dat data hold time [3] [4] [8] standard-mode 0 - s fast-mode 0 - s fast-mode plus 0 - s t su;dat data set-up time [9] [10] standard-mode 250 - ns fast-mode 100 - ns fast-mode plus 50 - ns
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 54 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller [8] the maximum t hd;dat could be 3.45 s and 0.9 s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time (see um10204 ). this maximum must only be met if th e device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [9] t su;dat is the data set-up time that is measured with respect to the rising edge of scl; applies to data in transmission and the acknowledge. [10] a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system but the requirement t su;dat = 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stre tch the low period of the scl signal, it must output the next data bit to the sda line t r(max) + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. al so the acknowledge timing must meet this set-up time. fig 28. i 2 c-bus pins clock timing 002aaf425 t f 70 % 30 % sda t f 70 % 30 % s 70 % 30 % 70 % 30 % t hd;dat scl 1 / f scl 70 % 30 % 70 % 30 % t vd;dat t high t low t su;dat
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 55 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 10.7 ssp0/1 interface remark: the ssp1 interface is available on the lpc1313fbd48/01 only. [1] t cy(clk) = (sspclkdiv (1 + scr) cpsdvsr) / f main . the clock cycle time deriv ed from the spi bit rate t cy(clk) is a function of the main clock frequency f main , the ssp peripheral clock divider (sspclkdiv), the ssp scr parameter (specified in the ssp0cr0 register), and the ssp cpsdvsr parameter (spec ified in the ssp clock prescale register). [2] t amb = ?40 c to +85 c. [3] t cy(clk) = 12 t cy(pclk) . [4] t amb = 25 c; v dd = 3.3 v. table 19. dynamic characteristics: ssp pins in spi mode symbol parameter conditions min max unit ssp master t cy(clk) clock cycle time full-duplex mode [1] 40 - ns when only transmitting [1] 27.8 - ns t ds data set-up time in spi mode; 2.4 v v dd 3.6 v [2] 15 - ns 2.0 v v dd < 2.4 v [2] 20 - ns t dh data hold time in spi mode [2] 0- n s t v(q) data output valid time in spi mode [2] -1 0n s t h(q) data output hold time in spi mode [2] 0- n s ssp slave t cy(pclk) pclk cycle time 13.9 - ns t ds data set-up time in spi mode [3] [4] 0- n s t dh data hold time in spi mode [3] [4] 3 t cy(pclk) + 4 - ns t v(q) data output valid time in spi mode [3] [4] -3 t cy(pclk) + 11 ns t h(q) data output hold time in spi mode [3] [4] -2 t cy(pclk) + 5 ns
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 56 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller fig 29. ssp master timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh data valid data valid t h(q) data valid data valid t v(q) cpha = 1 cpha = 0 002aae829
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 57 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller fig 30. ssp slave timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh t v(q) data valid data valid t h(q) data valid data valid cpha = 1 cpha = 0 002aae830
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 58 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 10.8 usb interface (lpc1342/43 only) [1] characterized but not implemented as production test. guaranteed by design. table 20. dynamic characteris tics: usb pins (full-speed) c l = 50 pf; r pu = 1.5 k on d+ to v dd , unless otherwise specified. 3.0 v v dd 3.6 v symbol parameter conditions min typ max unit t r rise time 10 % to 90 % 8.5 - 13.8 ns t f fall time 10 % to 90 % 7.7 - 13.7 ns t frfm differential rise and fall time matching t r /t f --1 0 9% v crs output signal crossover voltage 1.3 - 2.0 v t feopt source se0 interval of eop see figure 31 160 - 175 ns t fdeop source jitter for differential transition to se0 transition see figure 31 ? 2-+5ns t jr1 receiver jitter to next transition ? 18.5 - +18.5 ns t jr2 receiver jitter for paired transitions 10 % to 90 % ? 9-+9ns t eopr1 eop width at receiver must reject as eop; see figure 31 [1] 40 - - ns t eopr2 eop width at receiver must accept as eop; see figure 31 [1] 82 - - ns fig 31. differential da ta-to-eop transition skew and eop width 002aab561 t period differential data lines crossover point source eop width: t feopt receiver eop width: t eopr1 , t eopr2 crossover point extended differential data to se0/eop skew n t period + t fdeop
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 59 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 11. application information 11.1 suggested usb interface solutions (lpc1342/43 only) 11.2 xtal input the input voltage to the on-chip oscillators is limited to 1.8 v. if the oscillator is driven by a clock in slave mode, it is recommended that th e input be coupled through a capacitor with c i = 100 pf. to limit the input voltage to the specified range, choose an additional capacitor to ground c g which attenuates the input voltage by a factor c i /(c i + c g ). in slave mode, a minimum of 200 mv(rms) is needed. fig 32. lpc1342/43 usb interface on a self-powered device lpc134x usb-b connector usb_dp usb_connect soft-connect switch usb_dm usb_vbus v ss v dd r1 1.5 k r s = 33 002aae608 r s = 33 fig 33. lpc1342/43 usb interface on a bus-powered device lpc134x v dd r1 1.5 k 002aae609 usb-b connector usb_dp usb_dm usb_vbus v ss r s = 33 r s = 33
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 60 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller in slave mode the input clock signal should be coupled by means of a capacitor of 100 pf ( figure 34 ), with an amplitude between 200 mv(rms) and 1000 mv(rms). this corresponds to a square wave signal with a signal swing of between 280 mv and 1.4 v. the xtalout pin in this configur ation can be left unconnected. external components and models used in oscillation mode are shown in figure 35 and in ta b l e 2 1 and ta b l e 2 2 . since the feedback resistance is integrated on chip, only a crystal and the capacitances c x1 and c x2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequenc y is represen ted by l, c l and r s ). capacitance c p in figure 35 represents the parallel package capacitance and should not be larger than 7 pf. parameters f osc , c l , r s and c p are supplied by the crystal manufacturer. fig 34. slave mode operation of the on-chip oscillator fig 35. oscillator modes and models: oscillation mode of operation and external crystal model used for c x1 /c x2 evaluation lpc1xxx xtalin c i 100 pf c g 002aae788 002aaf424 lpc1xxx xtalin xtalout c x2 c x1 xtal = c l c p r s l
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 61 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 11.3 xtal printed-circuit bo ard (pcb) layout guidelines the crystal should be connected on the pcb as close as poss ible to the oscillator input and output pins of the chip. take care that the load capacitors c x1 , c x2 , and c x3 in case of third overtone crystal usage have a common ground plane. the external components must also be connected to the ground plain. loops must be made as small as possible in order to keep the noise coupled in via the pcb as small as possible. also parasitics should stay as small as possible. values of c x1 and c x2 should be chosen smaller accordingly to the increase in parasitics of the pcb layout. table 21. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) low frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2 1 mhz - 5 mhz 10 pf < 300 18 pf, 18 pf 20 pf < 300 39 pf, 39 pf 30 pf < 300 57 pf, 57 pf 5 mhz - 10 mhz 10 pf < 300 18 pf, 18 pf 20 pf < 200 39 pf, 39 pf 30 pf < 100 57 pf, 57 pf 10 mhz - 15 mhz 10 pf < 160 18 pf, 18 pf 20 pf < 60 39 pf, 39 pf 15 mhz - 20 mhz 10 pf < 80 18 pf, 18 pf table 22. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) high frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2 15 mhz - 20 mhz 10 pf < 180 18 pf, 18 pf 20 pf < 100 39 pf, 39 pf 20 mhz - 25 mhz 10 pf < 160 18 pf, 18 pf 20 pf < 80 39 pf, 39 pf
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 62 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 11.4 standard i/o pad configuration figure 36 shows the possible pin modes for standard i/o pins with analog input function: ? digital output driver ? digital input: pull-up enabled/disabled ? digital input: pull-down enabled/disabled ? digital input: repeater mode enabled/disabled ? analog input fig 36. standard i/o pad configuration pin v dd esd v ss esd v dd weak pull-up weak pull-down output enable repeater mode enable output pull-up enable pull-down enable data input analog input select analog input 002aaf304 pin configured as digital output driver pin configured as digital input pin configured as analog input
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 63 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 11.5 reset pad configuration 11.6 adc usage notes the following guidelines show how to increase the performance of the adc in a noisy environment beyond the adc specifications listed in ta b l e 8 : ? the adc input trace must be short and as cl ose as possible to the lpc1311/13/42/43 chip. ? the adc input traces must be shielded from fast switching digital signals and noisy power supply lines. ? because the adc and the digital core share the same power supply, the power supply line must be adequately filtered. ? to improve the adc performance in a very no isy environment, put the device in sleep mode during the adc conversion. fig 37. reset pad configuration v ss reset 002aaf274 v dd v dd v dd r pu esd esd 20 ns rc glitch filter pin
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 64 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 11.7 electromagnetic co mpatibility (emc) radiated emission measurements according to the iec61967-2 standard using the tem-cell method are shown for the lpc1343fbd48 in ta b l e 2 3 . [1] iec levels refer to appendix d in the iec61967-2 specification. table 23. electromagnetic compatibility (emc ) for part lpc1343fbd48 (tem-cell method) v dd = 3.3 v; t amb = 25 c. parameter frequency band system clock = unit 12 mhz 24 mhz 48 mhz 72 mhz input clock: irc (12 mhz) maximum peak level 150 khz - 30 mhz ? 6 ? 5 ? 7 ? 7db v 30 mhz - 150 mhz ? 1+3+9+13db v 150 mhz - 1 ghz +3 +7 +15 +19 db v iec level [1] -o nm l- input clock: crystal oscillator (12 mhz) maximum peak level 150 khz - 30 mhz -5 ? 5 ? 7 ? 7db v 30 mhz - 150 mhz 0 +4 +9 +13 db v 150 mhz - 1 ghz 3 +8 +15 +20 db v iec level [1] -o nm l-
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 65 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 12. package outline fig 38. package outline sot313-2 (LQFP48) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1)(1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 66 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller fig 39. package outline (hvqfn33) references outline version european projection issue date iec jedec jeita - - - hvqfn33_po 09-03-17 09-03-23 unit mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.2 7.1 7.0 6.9 4.85 4.70 4.55 7.1 7.0 6.9 0.65 4.55 0.75 0.60 0.45 0.1 a (1) dimensions note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm a 1 b 0.35 0.28 0.23 cd (1) d h e (1) e h 4.85 4.70 4.55 ee 1 e 2 4.55 lv 0.1 w 0.05 y 0.08 y 1 0 2.5 5 mm scale terminal 1 index area b a d e c y c y 1 x detail x a 1 a c b e 2 e 1 e e ac b v c w terminal 1 index area d h e h l 9 16 32 33 25 17 24 8 1
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 67 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 13. soldering fig 40. reflow soldering of the LQFP48 package sot313-2 dimensions in mm occupied area footprint information for reflow soldering of LQFP48 package ax bx gx gy hy hx ayby p1 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 10.350 p2 0.560 10.350 7.350 7.350 p1 0.500 0.280 c 1.500 0.500 7.500 7.500 10.650 10.650 sot313-2_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout p2
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 68 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller fig 41. reflow soldering of the hvqfn33 package footprint information for reflow soldering of hvqfn33 package 001aao134 occupied area solder land solder resist solder land plus solder paste solder paste deposit dimensions in mm remark: stencil thickness: 0.125 mm e = 0.65 evia = 4.25 owdtot = 5.10 oa pid = 7.25 pa+oa oid = 8.20 oa 0.20 sr chamfer (4) 0.45 dm evia = 1.05 w = 0.30 cu evia = 4.25 evia = 2.40 lbe = 5.80 cu lbd = 5.80 cu pie = 7.25 pa+oa lae = 7.95 cu lad = 7.95 cu oie = 8.20 oa owetot = 5.10 oa ehs = 4.85 cu dhs = 4.85 cu 4.55 sr 4.55 sr b-side (a-side fully covered) number of vias: 20 solder resist covered via 0.30 ph 0.60 sr cover 0.60 cu sehtot = 2.70 sp sdhtot = 2.70 sp gape = 0.70 sp spe = 1.00 sp 0.45 dm spd = 1.00 sp gapd = 0.70 sp
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 69 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 14. abbreviations table 24. abbreviations acronym description a/d analog-to-digital adc analog-to-digital converter ahb advanced high-performance bus amba advanced microcontroller bus architecture apb advanced peripheral bus bod brownout detection eop end of packet etm embedded trace macrocell fifo first-in, first-out gpio general purpose input/output hid human interface device i/o input/output lsb least significant bit msc mass storage class phy physical layer pll phase-locked loop se0 single ended zero spi serial peripheral interface ssi serial synchronous interface ssp synchronous serial port sof start-of-frame tcm tightly-coupled memory ttl transistor-transistor logic uart universal asynchronous receiver/transmitter usb universal serial bus
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 70 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 15. revision history table 25. revision history document id release date data sheet status change notice supersedes lpc1311_13_42_43 v.5 20120606 product data sheet - lpc1311_13_42_43 v.4 modifications: ? parameters v ol , v oh , i ol , i oh updated for voltage range 2.0 v v dd < 2.5 v in table 7 . ? condition ?the peak current is limited to 25 times the corresponding maximum current.? removed from parameters i dd and i ss in ta b l e 6 . lpc1311_13_42_43 v.4 20110620 product data sheet - lpc1311_13_42_43 v.3 lpc1311_13_42_43 v.3 20100810 product data sheet - lpc1311_13_42_43 v.2 lpc1311_13_42_43 v.2 20100506 product data sheet - lpc1311_13_42_43 v.1 lpc1311_13_42_43 v.1 20091211 product data sheet - -
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 71 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 16.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 16.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 72 of 74 nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 16.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 17. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
lpc1311_13_42_43 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 5 ? 6 june 2012 73 of 74 continued >> nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 7 functional description . . . . . . . . . . . . . . . . . . 17 7.1 architectural overview . . . . . . . . . . . . . . . . . . 17 7.2 arm cortex-m3 processor . . . . . . . . . . . . . . . 17 7.3 on-chip flash program memo ry . . . . . . . . . . . 17 7.4 on-chip sram . . . . . . . . . . . . . . . . . . . . . . . . 17 7.5 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.6 nested vectored interrupt controller (nvic) . 18 7.6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.6.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 19 7.7 ioconfig block . . . . . . . . . . . . . . . . . . . . . . 19 7.8 fast general purpose parallel i/o . . . . . . . . . . 19 7.8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.9 usb interface (lpc1342/43 only) . . . . . . . . . 20 7.9.1 full-speed usb device controller . . . . . . . . . . 20 7.9.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.10 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.11 ssp serial i/o controller . . . . . . . . . . . . . . . . . 21 7.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.12 i 2 c-bus serial i/o controller . . . . . . . . . . . . . . 21 7.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.13 10-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.14 general purpose external event counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.15 system tick timer . . . . . . . . . . . . . . . . . . . . . . 23 7.16 watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 23 7.16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.17 windowed watchdog timer (wwdt) . . . . . . 24 7.17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.18 clocking and power control . . . . . . . . . . . . . . 24 7.18.1 integrated oscillators . . . . . . . . . . . . . . . . . . . 24 7.18.1.1 internal rc oscillator . . . . . . . . . . . . . . . . . . . 25 7.18.1.2 system oscillator . . . . . . . . . . . . . . . . . . . . . . 26 7.18.1.3 watchdog oscillator . . . . . . . . . . . . . . . . . . . . 26 7.18.2 system pll and usb pll . . . . . . . . . . . . . . . 26 7.18.3 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.18.4 wake-up process . . . . . . . . . . . . . . . . . . . . . . 26 7.18.5 power control . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.18.5.1 power profiles (lpc1300l series, lpc1311/01 and lpc1313/01 only) . . . . . . . 27 7.18.5.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.18.5.3 deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 27 7.18.5.4 deep power-down mode . . . . . . . . . . . . . . . . 28 7.19 system control . . . . . . . . . . . . . . . . . . . . . . . . 28 7.19.1 start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.19.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.19.3 brownout detection . . . . . . . . . . . . . . . . . . . . 28 7.19.4 code security (code read protection - crp) 28 7.19.5 boot loader. . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.19.6 apb interface . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.19.7 ahb-lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.19.8 external interr upt inputs . . . . . . . . . . . . . . . . . 29 7.19.9 memory mapping control . . . . . . . . . . . . . . . . 29 7.20 emulation and debugging . . . . . . . . . . . . . . . 30 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 31 9 static characteristics . . . . . . . . . . . . . . . . . . . 32 9.1 bod static characterist ics for lpc1300 series 38 9.2 bod static characteri stics for lpc1300l series (lpc1311/01 and lpc1313/01). . . . . . . . . . . 39 9.3 power consumption for lpc1300 series . . . . 39 9.4 power consumption for lpc1300l series (lpc1311/01 and lpc1313/01). . . . . . . . . . . 42 9.5 peripheral power consumption . . . . . . . . . . . 45 9.6 electrical pin characteristics. . . . . . . . . . . . . . 46 10 dynamic characteristics. . . . . . . . . . . . . . . . . 50 10.1 power-up ramp conditions . . . . . . . . . . . . . . . 50 10.2 flash memory . . . . . . . . . . . . . . . . . . . . . . . . 50 10.3 external clock. . . . . . . . . . . . . . . . . . . . . . . . . 51 10.4 internal oscillators . . . . . . . . . . . . . . . . . . . . . 52 10.5 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.6 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.7 ssp0/1 interface . . . . . . . . . . . . . . . . . . . . . . 55 10.8 usb interface (lpc1342/43 only) . . . . . . . . . 58 11 application information . . . . . . . . . . . . . . . . . 59 11.1 suggested usb interface solutions (lpc1342/43 only) . . . . . . . . . . . . . . . . . . . . . 59 11.2 xtal input . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.3 xtal printed-circuit board (pcb) layout guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.4 standard i/o pad configuration . . . . . . . . . . . 62 11.5 reset pad configuration . . . . . . . . . . . . . . . . . 63 11.6 adc usage notes. . . . . . . . . . . . . . . . . . . . . . 63 11.7 electromagnetic compatibility (emc) . . . . . . 64
nxp semiconductors lpc1311/13/42/43 32-bit arm cortex-m3 microcontroller ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 6 june 2012 document identifier: lpc1311_13_42_43 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 65 13 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 69 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 70 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 71 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 71 16.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 16.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 72 17 contact information. . . . . . . . . . . . . . . . . . . . . 72 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

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